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System HW Principal Engineer, Holographic Display

San Jose, CA

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HW Systems Engineer with a very cutting edge holographic display start-up in San Jose CA.

Company is working on real Holography, w/ no Headgear. Recently raised around~$30MM in seed from top venture firms and Strategic Partners. Team has experience in all aspects of the ecosystem, but sees the linchpin as the display hardware so that is our primary focus at this time. Primary belief of the Company is that shared experiences can only be meaningfully driven with Holography.

To make Holography work, many pixels are needed (think Gigapixels). Supporting a multi-Gigapixel Holographic display requires new technology, and we have a large IP portfolio in support of the innovations required. One such area of innovation is the mechanisms to drive the correct light emissions to support the visual acuity of the human eye. Ultimately, we envision enabling myriad applications, including the concept of a true Holodeck, similar to what has been visualized in science fiction. Need team members who want to be part of the next step is visual display.

Vinod Khosla, Founder, Khosla Ventures: “This is essentially the holy grail of optical display technology, enabling things that seem like science fiction to be possible today. We are thrilled to be in on the ground floor with the team, and look forward to helping evolve this exciting technology”.


The System HW Principal Engineer will be responsible for design and implementation of HW for the world’s highest resolution holographic display ecosystem.  The ideal candidate has a background in imaging or display systems, and is familiar with implementing video interfaces in FPGAs.  He or she is able to specify detailed block diagrams for the interconnection between CPUs, PCIe devices, FPGAs, GPUs, and memory devices in a distributed system.  The candidate will be able to optimize these HW blocks for the most efficient video rendering solution for a real-time system.  The candidate will work daily with a team of software developers, EEs, mechanical engineers, optical engineers, other HW engineers, and experts in light field imaging.



Essential Duties and Responsibilities

  • Generate system-level HW architecture diagrams, and take a lead role in the implementation of a distributed display system which includes multiple servers driving a modular video display system with many gigapixels of resolution.
  • Lead the design and implementation of a custom distributed real-time engine which uses a balance of CPU and GPU functionality optimized to render video for a large light field display system.
  • Take a lead role in the design and implementation of custom FPGAs which employ video interface IP blocks, custom codecs, and communication with GPUs.
  • Work with the SW Systems Principal Engineer and the Computational Imaging Architect to achieve an optimal system-level design.
  • Implement proprietary codecs in processors, GPUs, and FPGAs
  • Other tasks as assigned.

Other Duties and Responsibilities

  • Work with software engineers, ME’s, optical engineers, and light field imaging experts to arrive at the optimal system requirements and implementation.
  • Evaluate new display technology, and work with GPU vendors to maximize their performance.



  • At least 5 years of experience in taking a lead role in the system level architecture and hardware implementation of complex video display systems. Experience with the design of imaging or display systems is a plus.
  • Able to specify complete system level as well as detailed block diagrams for the interconnection between CPUs, PCIe devices, FPGAs, GPUs, and memory devices in a distributed system.



  • Direct hands-on experience with tool chains for HDL, test bench, synthesis, place and route, timing analysis and closure for large high speed complex FPGAs. Verilog experience a plus.


  • Familiar with the design and implementation of video interface IP blocks in an FPGA, such as Display Port.


  • Experience with embedded processors.


  • Knowledgeable about video synchronization across multiple displays, and video timing signals.


  • Proven experience in working with software engineers to bring up a complex system.


  • Familiar with implementation of video encoding and decoding protocols in both HW and SW.


  • Experience with large-scale distributed systems.


  • Experience writing low-level HW drivers in FW is a plus.


  • Experience with implementing an FPGA PCIe interface to communicate with a host PCIe bus is a plus.


  • Comfortable in a fast-paced startup environment

Key Competencies

  • HW architecture detailing system design with CPUs, GPUs, and FPGAs


  • Design flow for large FPGAs.


  • Display Port IP blocks


  • Embedded processors


  • Video timing and synchronization across multiple displays


  • Video codecs


  • Distributed systems


  • Low-level HW drivers


  • PCIE communication between a target and a host CPU system